1. Field
The present invention relates to an amplifying apparatus and a bias stabilization circuit.
2. Description of the Related Art
FIG. 1 depicts an example of an amplifying apparatus 100. The amplifying apparatus 100 includes an amplifier 101 and a bias Gm compensation circuit 102. The amplifier 101 includes a first FET (Field Effect Transistor) FET1 (104), a second FET FET2 (106), and a load resistance R. The drain of the first FET FET1 (104) is connected to an output terminal OUT of the amplifier 101 via the second FET FET2 (106). The source of the first FET FET1 (104) is connected to a low voltage source. The gate of the first FET FET1 (104) is connected to a signal source S via a capacitor 110. Furthermore, bias is provided to the gate from the bias Gm compensation circuit 102.
The change ΔIamp of current flowing in the first FET FET1 (104) is proportional to the change of a gate voltage Vin in small signal region. The proportional coefficient is referred to as transconductance and is expressed as:ΔIamp=Gm×ΔVin
Accordingly, the voltage change ΔVout which is applied to the load resistance is expressed as:ΔVout=R×ΔIamp=R×Gm×ΔVin
The gain of the amplifying apparatus 100 is defined as R×Gm. The bias Gm compensation circuit 102 applies a suitable bias to the gate of the FET (104) for ensuring that the transconductance of the first FET FET1 (104) is in inverse proportion with respect to the load resistance R. Setting the gain R×Gm to be a constant value reduces the inconsistency of transfer characteristics due to, for example, temperature change in the manufacturing process of the FET or during operation of the FET. This is because a same type of resistance R in an integrated circuit LSI changes in the same manner with respect to, for example, changes in a manufacturing process. For example, Japanese Laid-Open Patent Application No. 2002-185288 (paragraph [0030], FIG. 9) discloses an example of a bias circuit having a FET with a transconductance Gm that is in inverse proportion with respect to the load resistance R.
FIG. 2 depicts a relationship between a drain current and a drain voltage of the first FET FET1 (104) shown in FIG. 1. In a case where a resistance RDS between a source and drain of a FET is relatively large, the drain current hardly changes even if there is a large change in the drain voltage. That is, ΔI with respect to the ΔV is considerably small so that it can be ignored. Therefore, even if the drain voltage V1 of the first FET FET1 large changes, the current Iamp flowing in each FET is hardly affected. Although the transconductance Gm of the FET changes if the current Iamp flowing in the FET changes, the change in the gain is small since the Iamp does not easily change.
As the resistance RDS between the source and drain become relatively smaller as the sizes of transistors become finer, change of drain current corresponding to change of drain voltage is becoming an aspect that cannot be ignored. In other words, ΔI with respect to ΔV is becoming relatively large. Therefore, the current Iamp changes in correspondence with the second FET FET2 (106), and the voltage and current of the drain of the first FET FET1 (104) also easily changes. When the drain current Iamp changes due to changes during a manufacturing process or operating temperature, the gain of the amplifying apparatus 100 also changes. Particularly, in a case where there is an inconsistency in the value of the threshold voltage Vth of the second FET FET2 (106) due to, for example, changes in the manufacturing process, the gain of the amplifier 101 is liable to become significantly inconsistent.